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Digital in-situ biasing technique

A highly digital in-situ biasing solution for analogue interfaces in nanoscale complementary metal-oxide semiconductor (CMOS) technologies is presented. The digital biasing scheme uses a time-based successive approximation conversion to provide the desired analogue functions with the voltage/current input and output. The digital biasing circuit obtains benefits from scaled devices with a small dimension and a high Ft, but with no design difficulties by the advanced CMOS process. By taking advantage of ultra-compact digital logic for control and adaptation, the digital biasing circuit does not suffer from the impact of intra-die variations since it eliminates the need for shared biasing approaches. A digital common-mode feedback circuit (CMFB) for a fully differential amplifier was simulated to demonstrate the advantages of the digital in-situ biasing scheme. The digital CMFB designed in a 65 nm CMOS process provides a desired output common-mode voltage as a conventional analogue CMFB, but does not need any stability compensation schemes. Compared with the analogue CMFB, the digital CMFB with the digital-like structure is more robust, has much smaller area, and does not require large passive components.

Comparison of the electronic structure of amorphous versus crystalline indium gallium zinc oxide semiconductor: structure, tail states and strain effects

We study the evolution of the structural and electronic properties of crystalline indium gallium zinc oxide (IGZO) upon amorphization by first-principles calculation. The bottom of the conduction band (BCB) is found to be constituted of a pseudo-band of molecular orbitals that resonate at the same energy on different atomic sites. They display a bonding character between the s orbitals of the metal sites and an anti-bonding character arising from the interaction between the oxygen and metal s orbitals. The energy level of the BCB shifts upon breaking of the crystal symmetry during the amorphization process, which may be attributed to the reduction of the coordination of the cationic centers. The top of the valence band (TVB) is constructed from anti-bonding oxygen p orbitals. In the amorphous state, they have random orientation, in contrast to the crystalline state. This results in the appearance of localized tail states in the forbidden gap above the TVB. Zinc is found to play ...

Characterization of interface trap dynamics responsible for hysteresis in organic thin-film transistors

Publication date: December 2015 Source:Organic Electronics, Volume 27 Author(s): Yin Sun, Lining Zhang, Zubair Ahmed, Mansun Chan In this paper, the current hysteresis of organic thin film transistors (OTFTs) formed by TIPS-Pentacene has been demonstrated by bi-directional gate-voltage scan and explained using the trapping and detrapping mechanism. The trapping and detrapping rates have been further verified by the gate-voltage sampling method and the channel charge pumping method. The validity of the methods to characterize interface states of OTFTs that lead to the hysteresis is justified. The two independent methods consistently reveal that the hole trapping and release rates at the interface between the channel of the OTFTs to the gate dielectric are asymmetric. Graphical abstract

Effect of GaN surface treatment on Al2O3/n-GaN MOS capacitors

The surface preparation for depositing Al2O3 for fabricating Au/Ni/Al2O3/n-GaN (0001) metal oxide semiconductor (MOS) capacitors was optimized as a step toward realization of high performance GaN MOSFETs. The GaN surface treatments studied included cleaning with piranha (H2O2:H2SO4 = 1:5), (NH4)2S, and 30% HF etches. By several metrics, the MOS capacitor with the piranha-etched GaN had the best characteristics. It had the lowest capacitance–voltage hysteresis, the smoothest Al2O3 surface as determined by atomic force microscopy (0.2 nm surface roughness), the lowest carbon concentration (∼0.78%) at the Al2O3/n-GaN interface (from x-ray photoelectron spectroscopy), and the lowest oxide-trap charge (QT = 1.6 × 1011 cm−2eV−1). Its interface trap density (Dit = 3.7 × 1012 cm−2eV−1), as measured with photon-assisted capacitance– voltage method, was the lowest from conduction band-edge to midgap.

Above-Threshold $1!/!f$ Noise Expression for Amorphous InGaZnO Thin-Film Transistors Considering Series Resistance Noise

The $1/f$ noise expression is presented for the amorphous InGaZnO thin-film transistors (TFTs) at low drain voltage. Considering the mobility power-law parameter $alpha $ in the TFTs, Ghibaudo’s carrier number fluctuation model with the series resistance noise is applied to obtain the analytical normalized drain current noise power spectral density expression. The expression is compared with the numerical calculation, and verified by the available experimental data.

Investigation of Hydration Reaction-Induced Protons Transport in Etching-Stop a-InGaZnO Thin-Film Transistors

In this letter, protons (hydrogen ions, H+ ions) transport-induced unstable transient electrical characteristics were found and studied in the etching-stop-layer in via-contact-type amorphous-indium–gallium–zinc-oxide thin-film transistors (a-IGZO TFTs) for the first time. By applying negative gate bias stress, more water molecules will be absorbed on the surface of the passivation layer, and thus the transmission of net protons in the etching-stop will increase. The proton transport model established in this letter can effectively analyze the a-IGZO TFTs instability using the threshold voltage ( $V_{T})$ determined from the current–voltage measurements, and which is unstable in a moist environment.

Modeling and Characterization of the Abnormal Hump in n-Channel Amorphous-InGaZnO Thin-Film Transistors After High Positive Bias Stress

Hump characteristics of n-channel amorphous indium-gallium–zinc-oxide (a-InGaZnO) thin-film transistors (TFTs) after positive gate and drain bias stress (PGDBS) are investigated. With the increase of the PGDBS time, we observed not only a shift of the threshold voltage ( $V_{T}$ ) but also a generation of the hump in the transfer characteristics. The hump is caused by the localized trapping of electrons in the gate insulator over the gate-source overlap region by the high vertical field during the PGDBS ( $V_{mathrm {GS}}=30$ , $V_{mathbf {DS}}=30$ ; $V_{mathrm {GD}}=V_{mathrm {GS}}-V_{mathrm {DS}}=0$ V). The TFT with a hump after PGDBS is modeled as a series connection of main and parasitic TFTs. The parasitic TFT for the electron trapping at the gate-source overlap region has a higher threshold voltage ( $V_{mathrm {Tp}}$ ) and a shorter effective channel length ( $L_{mathrm {chp}}cong L_{mathrm {ov}}$ ) compared with those ( $V_{mathrm {Tm}}$ and $L_{mathrm {ch}}$ ) of the main TFT.

Extraction of Trap Densities in Amorphous In-Ga-Zn-O Thin-Film Transistors by Using Efficient Surface Potential Calculations

A novel extraction method for trap densities in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is developed. In this method, a new calculation procedure for efficiently determining surface potentials (SPs) in the a-IGZO layer is used with low-frequency capacitance-voltage ( $C$ - $V$ ) measurements. To enhance the computational efficiency of the extraction method, we propose an approximate expression relating the front-side and back-side SPs, so that it is possible to determine SPs without conventionally required calculation steps, such as either meshing the a-IGZO layer or calculating the potential profiles for the entire layer. The extraction method is tested by using low-frequency $C$ - $V$ curves of a self-aligned a-IGZO TFT to minimize the influence of parasitic capacitances and resistances. This method is expected to facilitate the extraction of trap densities, and contribute to characterization and modeling of a-IGZO TFTs.

On the Origin of Improved Charge Transport in Double-Gate In–Ga–Zn–O Thin-Film Transistors: A Low-Frequency Noise Perspective

Low-frequency noise (LFN) in double-gate (DG) In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) is studied to investigate the origin of performance improvement. We found that thinning down the IGZO film enhances such improvements. With 7-nm IGZO, the mobility is raised by a factor of 3.77, and the subthreshold slope is reduced to 0.17 V/decade from single-gate to DG mode. Device simulations show that bulk transport inside IGZO film emerges as the two gates field effects get coupled. The LFN results reveal a transport transition from surface to bulk and disclose the superior bulk transport that experiences slight phonon scattering with a small Hooge parameter $alpha _{H }= 4.44 times 10^{mathrm {-3}}$ , whereas the surface transport undergoes serious charge trapping with surface trap densities about $2 times 10^{11}$ eV $^{-1}$ cm $^{-2}$ .

Novel Multi-Level Cell TFT Memory With an In–Ga–Zn-O Charge Storage Layer and Channel

Amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor nonvolatile memory devices with an IGZO charge storage layer were evaluated for the first time for multi-level cell memory applications. The pristine device was defined as the original state (OS), which can be switched to the programmed state (PS) after a positive gate voltage pulse (for example, 12 V for 10 ms), and to the erased state (ES) after a negative gate voltage pulse (for example, −15 V for 10 ms). The writing mechanism was attributed to Fowler–Nordheim tunneling of electrons from the channel to the charge storage layer under a positive gate bias and inverse tunneling under a negative gate bias. The devices demonstrated superior electrical programmable and erasable characteristics. A memory window of 2.4 V between OS and PS was maintained after 100 programming/erasing cycles, and a memory window of 2.66 V between OS and ES as well. The memory windows relative to OS are equal to 1.91 and 1.30 V for PS and ES, respectively, for a retention time of $10^{5}$ s.