Publication date: 1 October 2015 Source:Thin Solid Films, Volume 592, Part A Author(s): Yongyue Chen, Yajie Sun, Xusheng Dai, Bingpo Zhang, Zhenyu Ye, Miao Wang, Huizhen Wu Oxide p-type transistors are expected in realization of complementary circuits. Here, amorphous p-type NiO thin films were deposited on glass substrates by radio frequency (rf) sputtering at various growth temperatures and O2/Ar flow ratios. The influence of growth temperature and O2/Ar flow ratio on the structural and electrical properties of amorphous NiO thin films has been systematically investigated by means of characterizations from X-ray diffraction, UV–vis spectroscopy, and electrical measurements. Pure Ar ambient with room temperature (RT) growth of NiO films shows the highest mobility of 1.07cm2/Vs, and hole concentration of 2.78×1017 cm−3. Initial p-type NiO-based thin film transistors grown by magnetron sputtering demonstrated a mobility of 0.05cm2/Vs, a threshold voltage (Vth) of −8.6V, subthreshold swing (S) of 2.6V/dec, the current on–off ratio of 103, respectively.
In this reported work, amorphous InGaZnO thin film transistors (TFTs) with symmetric and asymmetric structures are fabricated. A constant positive gate bias for a time of 1–5 × 104 s was then applied to the TFTs to investigate their performance variation. The mobilities of the TFTs were not significantly degraded by a long stress time of 5 × 104 s. Also, decreases of sub-threshold swing and off-state current were observed for a stress time of 104 s. Although significant threshold voltage variation was found for the a-IGZO TFT with a symmetric design during the stress test, it could be reduced by 56% for the TFT fabricated by the proposed asymmetric design.
ZnO is promising for a number of applications in light emission, sensors, and transparent conducting electronics, but its surface is susceptible to instabilities caused by atmospheric exposure. Thus, there is a need for stable passivation or gate dielectric layers that might obviate this issue. One potential candidate is Sc2O3. The authors have measured the band offsets of sputtered Sc2O3 on both Zn- and O-terminated ZnO using x-ray photoelectron spectroscopy and obtained the bandgaps of the materials using reflection electron energy loss spectroscopy. The valence band offset was determined to be ∼1.67 ± 0.16 eV for Sc2O3 on Zn-terminated ZnO (bandgap 3.26 eV) and 1.59 ± 0.16 eV on O-terminated ZnO (bandgap 3.22 eV), i.e., similar within experimental error. The conduction band offset for Sc2O3/ZnO was then determined to be 4.92 eV. The Sc2O3/ZnO system has a staggered, type II alignment, meaning that it is not suitable for thin film transistors but it may still be useful for surface passivation.
J. Mater. Chem. C, 2015, Advance ArticleDOI: 10.1039/C5TC01951F, CommunicationYang Xi, Lidia El Bouanani, Zhe Xu, Manuel A. Quevedo-Lopez, Majid Minary-JolandanThin film transistors fabricated using ZnSe thin films synthesized using chemical bath deposition.To cite this article before page numbers are assigned, use the DOI form of citation above.The content of this RSS Feed (c) The Royal Society of Chemistry
This paper performs an experimental comparative study of the total ionizing dose effects due to the x-ray radiation between the silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) manufactured with octagonal gate geometry and the standard counterpart. Our main focus is on integrated transceivers for wireless communications and smart-power dc/dc converters for mobile electronics, where the transistor is used as the key switching element. It is shown that this innovative layout can reduce the total ionizing dose (TID) effects due to the special characteristics of the OCTO SOI MOSFET bird’s beak regions, where longitudinal electrical field lines in these regions are not parallel to the drain and source regions. Consequently, the parasitic MOSFETs associated with these regions are practically deactivated.
The authors present a facile, low-cost methodology to fabricate high-performance In-Ga-Zn-O (IGZO) bottom contact, bottom gate thin-film transistors (TFTs) by soft lithography. The IGZO channel and indium tin oxide (ITO) source and drain were patterned using microcontact printing of an octadecylphosphonic acid self-assembled monolayer (SAM). A polymer stamp was used for the pattern transfer of the SAMs, which were then used as a chemical protection layer during wet etching. Excellent pattern transfer was obtained with good resolution and sharp step profiles. X-ray photoelectron spectroscopy indicated that the microcontact printed SAMs can be effectively removed from the ITO source/drain surfaces, allowing a high-quality interface to the IGZO channel for good device performance. Scanning electron microscopy cross-sections of the devices indicate a smooth and defect-free transition regions between the source/drain and semiconductor regions. The fabricated TFTs have negligible gate-leakage currents, high average electron mobilities of 10.2 cm2/Vs, and excellent on-off ratios of 2.1 × 108. These results may provide new methodologies for low-cost and large-area integration of IGZO-TFTs for a range of applications including flexible and transparent displays.
Publication date: Available online 2 September 2015 Source:Thin Solid Films Author(s): Chang-Chun Lee, Chia-Ping Hsieh, Pei-Chen Huang, Sen-Wen Cheng, Ming-Han Liao The considerably high carrier mobility of Ge makes Ge-based channels a promising candidate for enhancing the performance of next-generation devices. The N-type metal-oxide semiconductor field-effect transistor (nMOSFET) is fabricated by introducing the epitaxial growth of high-quality Ge-rich Ge1-xSix alloys in source/drain (S/D) regions. However, the short channel effect is rarely considered in the performance analysis of Ge-based devices. In this study, the gate-width dependence of a 20 nm Ge-based nMOSFET on electron mobility is investigated. This investigation uses simulated fabrication procedures combined with the relationship of the interaction between stress components and piezoresistive coefficients at high-order terms. Ge1-xSix alloys, namely, Ge0.96Si0.04, Ge0.93Si0.07, and Ge0.86Si0.14, are individually tested and embedded into the S/D region of the proposed device layout and are used in the model of stress estimation. Moreover, a 1.0 GPa tensile contact etching stop layer (CESL) is induced to explore the effect of bi-axial stress on device geometry and subsequent mobility variation. Gate widths ranging from 30 nm to 4 μm are examined. Results show a significant change in stress when the width is <300 nm. This phenomenon becomes notable when the Si in the Ge1-xSix alloy is increased. The stress contours of the Ge channel confirm the high stress components induced by the Ge0.86Si0.14 stressor within the device channel. Furthermore, the stresses (Syy) of the channel in the transverse direction become tensile when CESL is introduced. Furthermore, when pure S/D Ge1-xSix alloys are used, a maximum mobility gain of 28.6% occurs with a ~70 nm gate width. A 58.4% increase in mobility gain is obtained when a 1.0 GPa CESL is loaded. However, results indicate that gate width is extended to 200 nm at this point.