Monthly Archives: July 2015

Large-Scale Precise Printing of Ultrathin Sol–Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays

Ultrathin and dense metal oxide gate di­electric layers are reported by a simple printing of AlOx and HfOx sol–gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm2 V−1 s−1 and gate leakage current of 10−9 A cm−2 at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes.

Highly Robust Flexible Oxide Thin-Film Transistors by Bulk Accumulation

We report the achievement of flexible oxide thin-film transistors (TFTs) that are highly robust under mechanical bending stress. Fabricated on solution-processed polyimide, the oxide TFTs employ the dual-gate structure with an amorphous-indium-gallium-zinc oxide (a-IGZO) semiconductor, silicon dioxide gate insulators, and molybdenum gate and source/drain electrodes. High mechanical stability is achieved by shorting the two gates together to induce bulk accumulation (BA)—a condition in which the channel accumulation layer of electrons extends the entire depth of the active layer. It is shown experimentally that the BA a-IGZO TFTs exhibit better stability under bending stress compared with single gate-driven TFTs. From TCAD simulations, the immunity to slight variations in carrier concentration under tensile strain is found to be a result of the high gate-drive intrinsic of the BA TFTs.

Improvement in Device Performance of a-InGaZnO Transistors by Introduction of Ca-Doped Cu Source/Drain Electrode

This letter reports the effects of Ca doping into Cu films, which was used as a source/drain (S/D) electrode for high performance amorphous In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) with a low resistive–capacitive delay time. The IGZO TFTs with Ca-doped Cu S/D exhibited three times higher saturation mobility (16 cm $^{2}$ /Vs) and substantially lower subthreshold gate swing of 0.39 V/decade than the control devices with pure Cu S/D. The SIMS profile and cross-sectional transmission electron microscopy showed that Ca effectively prevented the Cu atoms from diffusing into channel IGZO region presumably as a result of Ca–O bond formation, which is responsible for their superior device performances.

Film-Profile Engineered InGaZnO Thin-Film Transistors With Self-Aligned Bottom Gates

We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.

From non-detectable to decent: replacement of oxygen with sulfur in naphthalene diimide boosts electron transport in organic thin-film transistors (OTFT)

J. Mater. Chem. C, 2015, Advance ArticleDOI: 10.1039/C5TC01519G, PaperWangqiao Chen, Jing Zhang, Guankui Long, Yi Liu, Qichun ZhangWe demonstrated a dramatic enhancement of the electron mobility of naphthalene diimide in thin film transistors under ambient conditions using a simple step reaction replacing oxygen with sulfur atoms.To cite this article before page numbers are assigned, use the DOI form of citation above.The content of this RSS Feed (c) The Royal Society of Chemistry

Defect-induced optical and electrical property modification in amorphous InGaZnO4 films

Publication date: 15 October 2015 Source:Journal of Non-Crystalline Solids, Volume 426 Author(s): Hyegyeong Kim, Eunsang Hwang, Doo-Yong Lee, Ji-Woong Kim, Jungseek Hwang, Jong-Seong Bae, Jeong-Soo Lee, Sungkyun Park We report the physical characteristics of InGaZnO4 films deposited at various temperatures. The films were deposited on Al2O3(0001) substrates using pulsed laser deposition technique. Based on X-ray diffraction and field emission scanning electron microscopy measurements, the crystal structure changed from amorphous to polycrystalline as deposition temperature increased to 550°C. Furthermore, UV–vis measurements revealed a decrease in tail state i.e. improvement of local ordering, resulting in an increase of optical band-gap energy as deposition temperature increased. The core-level X-ray photoelectron spectra also showed an increase (decrease) in metal-oxide (oxygen deficiency) bond as the deposition temperature increased. The carrier concentration, Hall mobility and conductivity variation with deposition temperature are related to the competition between oxygen deficiency and grain boundary formation.

Mechanical and electrical stability of PEDOT:PTS and Au source/drain electrodes for bottom contact OTFTs on plastic films under bending conditions

Publication date: November 2015 Source:Organic Electronics, Volume 26 Author(s): Rahim Abdur, Young Kyu Lee, Kyunghoon Jeong, Ho-Seok Nam, Young-Ho Kim, Jiyoung Kim, Jaegab Lee Two types of source/drain (S/D) electrodes, formed of poly(3,4-ethylenedioxythiophene):p-toluenesulfonate (PEDOT:PTS) conducting polymer and Au, were fabricated and mounted on flexible pentacene transistors. Several properties of the S/D electrodes were investigated: the adhesion between electrode and pentacene, the failure induced by mechanical bending, the electrical properties including contact resistance, and the field-effect mobility. The measurement of adhesive force using a 90° peel tester revealed that the adhesive force of the pentacene–PEDOT:PTS interface was 200N/m, while that of Au–pentacene was too small to be measured. The poor adhesion between the Au and pentacene led to the local delamination of the Au film, starting at a strain of approximately 1% and with a rapid increase of delamination density with increasing strain. The strain-induced mechanical damage has a direct effect on contact resistance, which in turn degrades mobility. In contrast, no delamination is observed with the high adhesive force at the pentacene–PEDOT:PTS interface, which thus led to a slight increase of contact resistance and mobility with strain. Consequently, the pentacene–PEDOT:PTS contacts provide mechanical and electrical stability in flexible organic thin film transistors (OTFTs) under bending tests. Graphical abstract

Balancing the Lifetime and Storage Overhead on Error Correction for Phase Change Memory

by Ning An, Rui Wang, Yuan Gao, Hailong Yang, Depei Qian As DRAM is facing the scaling difficulty in terms of energy cost and reliability, some nonvolatile storage materials were proposed to be the substitute or supplement of main memory. Phase Change Memory (PCM) is one of the most promising nonvolatile memory that could be put into use in the near future. However, before becoming a qualified main memory technology, PCM should be designed reliably so that it can ensure the computer system’s stable running even when errors occur. The typical wear-out errors in PCM have been well studied, but the transient errors, that caused by high-energy particles striking on the complementary metal-oxide semiconductor (CMOS) circuit of PCM chips or by resistance drifting in multi-level cell PCM, have attracted little focus. In this paper, we propose an innovative mechanism, Local-ECC-Global-ECPs (LEGE), which addresses both soft errors and hard errors (wear-out errors) in PCM memory systems. Our idea is to deploy a local error correction code (ECC) section to every data line, which can detect and correct one-bit errors immediately, and a global error correction pointers (ECPs) buffer for the whole memory chip, which can be reloaded to correct more hard error bits. The local ECC is used to detect and correct the unknown one-bit errors, and the global ECPs buffer is used to store the corrected value of hard errors. In comparison to ECP-6, our method provides almost identical lifetimes, but reduces approximately 50% storage overhead. Moreover, our structure reduces approximately 3.55% access latency overhead by increasing 1.61% storage overhead compared to PAYG, a hard error only solution.