In this report, photo-induced hysteresis, threshold voltage (VT) shift, and recovery behaviors in photochemically activated solution-processed indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) are investigated. It was observed that a white light illumination caused negative VT shift along with creation of clockwise hysteresis in electrical characteristics which can be attributed to photo-generated doubly ionized oxygen vacancies at the semiconductor/gate dielectric interface. More importantly, the photochemically activated IGZO TFTs showed much reduced overall VT shift compared to thermally annealed TFTs. Reduced number of donor-like interface states creation under light illumination and more facile neutralization of ionized oxygen vacancies by electron capture under positive gate potential are claimed to be the origin of the less VT shift in photochemically activated TFTs.
Self-heating effect is recently considered to play an essential role in the degradation of amorphous oxide thin film transistors (TFTs). Previous thermal analysis on amorphous oxide TFTs based on conventional infrared thermography, however, had limitations in studying short-channel TFTs due to its low spatial-resolution. Here, we investigated self-heating effect of short-channel amorphous In-Ga-Zn-O TFTs by using high-resolution thermoreflectance microscopy. For the TFT with a channel length of 15 μm and a distance of 10.8 μm between source and drain electrodes on an etch stopper, the device temperature due to self-heating reached 70–80 °C, and local heating arose close to the center of the channel compared to the drain side in the literature. The channel length dependence of thermal distribution revealed that the asymmetry of local heating weakened with the decreasing channel length due to a heat dissipation by the source and drain electrodes. Transient thermal analysis under a bias stress unveiled that the maximum temperature as a function of stress time strongly depends on bias stress conditions. The temporal behavior of temperature is possibly attributed to the interaction between self-heating and local degradation.
Publication date: September 2014 Source:Organic Electronics, Volume 15, Issue 9 Author(s): Gamal A. Abbas , Ziqian Ding , Hazel E. Assender , John J. Morrison , Stephen G. Yeates , Eifion R. Patchett , D. Martin Taylor We report on the performance of organic thin film transistors manufactured in an all-evaporated vacuum roll-to-roll process. We show that dinaphtho [2,3-b:2′,3′-f] thieno[3,2-b]thiophene (DNTT) is a suitable semiconductor material for deposition onto a flash evaporated polymer insulator layer to make bottom-gate top-contact transistors. Significantly, in batches of 90 transistors, the process approached a 100% yield of high mobility transistors with high on/off ratios and low gate-leakage. By contrast, a solution-deposited insulator layer led to significant gate leakage in a high proportion of transistors leading to poor yield. The performance of DNTT devices is shown to be superior to that of previously reported pentacene devices. Transistor performance is further enhanced by inclusion of a low-polarity surface modification, such as polystyrene, to the acrylate. The devices show good environmental stability but we demonstrate also that they can be in-line encapsulated with an acrylate and a SiOx overlayer without damaging the underlying transistor. Finally, a first demonstration is made of organic vapour jet printing of the DNTT to manufacture transistors with a high semiconductor deposition rate. Graphical abstract Highlights
We propose a new active matrix organic light-emitting diode (AMOLED) pixel circuit in which the compensation for the thin film transistor and OLED performance variation and/or degeneration is performed periodically in a separate frame time. In the other frame time, the AMOLED pixel works without any compensation operation, so that the whole row time is used for driving. Only three transistors and two capacitors are required to construct the pixel circuit. It is demonstrated that both accurate compensation and high driving speed can be realized in the separate frame compensated AMOLED pixel circuit.
The emergence of new nonvolatile memory (NVM) technologies—such as phase change memory, resistive, and spin-torque-transfer magnetic RAM—has been motivated by exciting applications such as storage class memory, embedded nonvolatile memory, enhanced solid-state disks, and neuromorphic computing. Many of these applications call for such NVM devices to be packed densely in vast “crosspoint” arrays offering many gigabytes if not terabytes of solid-state storage. In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selected devices greatly exceed the residual leakage through the nonselected devices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic. This article reviews progress made toward implementing such access device functionality, focusing on the need to stack such crosspoint arrays vertically above the surface of a silicon wafer for increased effective areal density. The authors start with a brief overview of circuit-level considerations for crosspoint memory arrays, and discuss the role of the access device in minimizing leakage through the many nonselected cells, while delivering the right voltages and currents to the selected cell. The authors then summarize the criteria that an access device must fulfill in order to enable crosspoint memory. The authors review current research on various discrete access device options, ranging from conventional silicon-based semiconductor devices, to oxide semiconductors, threshold switch devices, oxide tunnel barriers, and devices based on mixed-ionic-electronic-conduction. Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM.
Publication date: September 2014 Source:Organic Electronics, Volume 15, Issue 9 Author(s): Yingtao Xie , Shucheng Cai , Qiang Shi , Shihong Ouyang , Wen-Ya Lee , Zhenan Bao , James R. Matthews , Robert A. Bellman , Mingqian He , Hon Hang Fong A compatible process of orthogonal self-assembled monolayers (SAMs) is applied to intentionally modify the bottom contacts and gate dielectric surfaces of organic thin film transistors (OTFTs). This efficient interface modification is first achieved by 4-fluorothiophenol (4-FTP) SAM to chemically treat the silver source–drain (S/D) contacts while the silicon oxide (SiO2) dielectric interface is further primed by either hexamethyldisilazane (HMDS) or octyltrichlorosilane (OTS-C8). Results show that the field effect mobilities of the bottom-gate bottom-contact PTDPPTFT4 transistors were significantly improved to 0.91cm2 V−1 s−1. Graphical abstract Highlights
Solution-processed ultra-thin (∼3 nm) zinc tin oxide (ZTO) thin film transistors (TFTs) with a mobility of 8 cm2/Vs are obtained with post spin-coating annealing at only 350 °C. The effect of light illumination (at wavelengths of 405 nm or 532 nm) on the stability of TFT transfer characteristics under various gate bias stress conditions (zero, positive, and negative) is investigated. It is found that the ΔVth (Vthstress 3400 s − stress 0 s) window is significantly positive when ZTO TFTs are under positive bias stress (PBS, ΔVth = 9.98 V) and positive bias illumination stress (λ = 405 nm and ΔVth = 6.96 V), but ΔVth is slightly negative under only light illumination stress (λ = 405 nm and ΔVth = −2.02 V) or negative bias stress (ΔVth = −2.27 V). However, the ΔVth of ZTO TFT under negative bias illumination stress is substantial, and it will efficiently recover the ΔVth caused by PBS. The result is attributed to the photo-ionization and subsequent transition of electronic states of oxygen vacancies (i.e., Vo, Vo+, and Vo++) in ZTO. A detailed mechanism is discussed to better understand the bias stress stability of solution processed ZTO TFTs.
In order to understand the electrical conduction mechanisms in the transfer characteristics of pentacene-based organic thin film transistors (OTFTs), an analysis using the temperature-dependent transfer characteristics is presented. The temperature-dependent transfer characteristics exhibit hopping conduction behavior. Compared to the fitting data for the temperature-dependent linear-regime (saturation-regime) transfer characteristics of OTFTs, the fitting data for the temperature-dependent sub-threshold-regime transfer characteristics of OTFTs show that a longer hopping distance and a higher barrier height for hopping result in a higher channel resistance. However, similar hopping conduction behavior is seen in the saturation and linear regions, which demonstrates that the carrier mobility is drain-source voltage-dependent.
Oxide thin film transistor employing copper source/drain electrodes shows a small turn on voltage and reduced hysteresis. Cross-sectional high-resolution transmission electron microscopy image confirmed the formation of ∼4 nm CuOx related interlayer. The lower bond-dissociation energy of Cu-O compared to Si-O and In-O suggests that the interlayer was formed by adsorbing oxygen molecules from surrounding environment instead of getting oxygen atoms from the semiconductor film. The formation of CuOx interlayer acting as an acceptor could suppress the carrier concentration in the transistor channel, which would be utilized to control the turn on voltage shifts in oxide thin film transistors.
Optically more stable, high mobility InGaZnO thin film transistors were fabricated by implementing ultrathin In2O3-SnO2 (ITO) layers at the gate dielectric/semiconductor interface. The optimized device portrayed a high saturation mobility of ∼80 cm2/V s with off current values lower than 10−11A. The ITO layer also acted as a hole filter layer, and hole current and threshold voltage shift values measured under negative bias illumination conditions showed that a significant amount of photo-generated charge carriers were annihilated before reaching the gate insulator. This effect was more evident at larger intensities, showing threshold voltage shift values reduced by more than ∼70% under stress conditions.